1. Field of the Invention
This invention generally relates to digital communications and, more particularly, to a system and method for interleaving and disinterleaving frames of words using frame alignment markers created from transcoding the words.
2. Description of the Related Art
Ethernet messages, either octets of data or control information, are redundantly encoded for the purpose of maintaining DC balance, which is also referred to as running disparity (RD), and ensuring sufficient edge density. 8 B/10 B is a common RD-encoded format. 8-bit symbols are mapped into 10-bit symbols, coded to provide a sufficient number of state changes to permit clock recovery from the data stream and to ensure DC balance. 8 B/10 B coding is used in applications such as PCI Express, IEEE 1394b, Fibre Channel, Gigabit Ethernet, InfiniBand, and XAUI to name but a few. 64 B/66 B is a similar format where 64 symbols are mapped into a 66-bit word. Using a system that controls long-term DC-balance and edge density permits a data stream to be transmitted through a channel with a high-pass characteristic, and to be recovered with conventional clock and data recovery (CDR) units.
More explicitly, 64 B/66 B is encoded with 2 extra bits per 64 data bits, to detect the start of a 66-bit block. Two bits are used to provide a sufficiently unique value to find the start of a block. To maintain DC balance the value is either 10 or 01. 01 indicates that the block is data, and 10 indicates that the block is control. However, if start of block is known, only one bit is required to identify control versus data type.
IEEE 802.3ba is a recent standard for 40 G (40 gigabit per second) Ethernet. Connections between devices on the same board may be achieved using the XLAUI, which uses 4 lanes of 10 G. Current interface technology in some applications (e.g., FPGA) does not support 10 G rates. A means to send data at a lower rate by using more lanes is required.
One solution to the above-mentioned problem would be to disinterleave a single high-speed physical lane into parallel physical lanes. Such an arrangement would permit backward compatibility, and permit the parallel lanes to be operated at a lower data rate. Further, the buffering requirement would be reduced. However, as presently devised, there are an insufficient number of frame alignment markers for disinterleaving a single lane into multiple lanes. Without frame alignment markers in each lane, the disinterleaved frames are difficult to recover.
IEEE 802.3ba explicitly supports 40 G with 4 lanes of 10 G each. However, there is not an explicit way to disinterleave one of the 4 lanes into two 5 G lanes compatible with current systems. Without frame alignment markers, such 5 G lanes cannot be re-interleaved at the receive side, especially if there is a temporal skew resulting from buffering at the Tx, differences in the lengths of the signal carrying media, or buffering at the Rx.
It would be advantageous if a frame of information in a redundantly encoded message format, such as 64 B/66 B, could be disinterleaved into parallel frames with their own frame alignment markers, and transmitted at the same (combined) rate as the original frame, without excessive latency and buffering requirements.